1. Field of the Invention
The present invention relates to a memory device for reducing leakage current, and more particularly to a memory device for reducing leakage current generated by a bridge between a word line and a bit line when the memory device is in a waiting mode.
2. Description of the Prior Art
With the high integration of a memory device, the space of a memory cell is reduced and the size of a pattern is also reduced according to the reduction. Therefore, the occurrence probability of a bridge may also increase between a word line and a bit line. A memory device typically includes a redundant cell and a bad memory cell generated by a bridge between a word line and a bit line, etc., is replaced with the redundant cell through a redundant operation. However, even though the bad memory cell generated by the bridge between the word line and the bit line is replaced with the redundant cell, leakage current may flow by the bridge between the word line and the bit line in a waiting mode of a memory device. Therefore, power may be consumed.
FIG. 1 is a circuit diagram illustrating one example of a case where a bridge is formed between a word line and a bit line in a conventional memory device.
As shown in FIG. 1, the memory device includes memory cell blocks 111 to 114, sense amp blocks 121 to 125, switching blocks 141 to 148, and controllers 171 to 174.
Hereinafter, cases where the memory device is in an operation mode and a waiting mode will be separately described.
When the memory device is in the operation mode, in order to designate matrix type memory cells, row addresses and column addresses are applied to the memory cells through word lines WL1 to WL4 and bit lines BL1, /BL1, BL2, /BL2, BL3, /BL3, BL4, and /BL4. Simultaneously, an enable signal ACT is applied to the controller 171 to 174. Then, the controller 171 applies a control signal BIS1 to the switching blocks 141 and 142, the controller 172 applies a control signal BIS2 to the switching blocks 143 and 144, the controller 173 applies a control signal BIS3 to the switching blocks 145 and 146, and the controller 174 applies a control signal BIS4 to the switching blocks 147 and 148. For example, when one memory cell block 112 is selected from the four memory cell blocks 111 to 114, only the control signal BIS2 comes into a low level from among the four control signals BIS1, BIS2, BIS3 and BIS4. Therefore, only two switching blocks 142 and 145 are turned off from among the eight switching blocks 141 to 148. As a result, the sense amp blocks 122 and 123 are connected to the memory cell block 112 to be selected. The sense amps 128 and 129 of the connected sense amp block 122 and the sense amps 130 and 131 of the connected sense amp block 123 detect data of the memory cells in the memory cell block 112, respectively. Specifically, the sense amp block described in FIGS. 1 and 2 includes an equalizer for precharging corresponding pairs of bit lines with precharge voltage. As known in the art, an equalizer is a circuit for precharging pairs of bit lines with precharge voltage (e.g., Vdd/2) in a precharge mode.
When the memory device is in the waiting mode, each of the word lines WL1 to WL4 maintains a ground level, i.e., a Vss level, and each of the bit lines BL1, /BL1, BL2, /BL2, BL3, /BL3, BL4, and /BL4 maintains a Vcc/2 level. The controller 171 applies the control signal BIS1 of a high level to the switching blocks 141 and 142 by the enable signal ACT, the controller 172 applies the control signal BIS2 of a high level to the switching blocks 143 and 144 by the enable signal ACT, the controller 173 applies the control signal BIS3 of a high level to the switching blocks 145 and 146 by the enable signal ACT, and the controller 174 applies the control signal BIS4 of a high level to the switching blocks 147 and 148 by the enable signal ACT. Therefore, all of the switching blocks 141 to 148 are turned on. That is, the memory cell block 111 is connected to the sense amp blocks 121 and 122, the memory cell block 112 is connected to the sense amp blocks 122 and 123, the memory cell block 113 is connected to the sense amp blocks 123 and 124, and the memory cell block 114 is connected to the sense amp blocks 124 and 125. Herein, because the bit line is maintained with the precharge voltage, leakage current is continuously generated from the bit line to the word line having the ground voltage through a defective cell transistor. That is, when a bridge 181 is formed between the word line WL2 and the bit line BL3, the leakage current flows from the bit line to the word line by voltage difference between the word line and the bit line because the switching block 144 is in the turn-on state.
The leakage current flows when the memory device is in the waiting mode, thereby consuming power. Specifically, this power consumption may be largely problematic in recent memory devices pursuing low power consumption.